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January 26, 1999 Preliminary
MSM9562/63/66/67
IC for FM Multiplex Demodulation User's Manual [Control Flow]
Oki Electric Co., Ltd.
Version 0.9
IMPORTANT NOTICE
DARC (DAta Radio Channel), an FM multiplex broadcast technology, has been developed by NHK (Japan Broadcasting Corporation). DARC is a registered trademark of NHK Engineering Service (NHK-ES). Any manufacturer who intends to manufacture/sell products that utilize DARC technology needs to be licensed by NHK-ES. For detailed information on licenses, please contact: NHK Engineering Service Phone: (+81) 3-3481-2650
DARC (DAta Radio Channel), an FM multiplex broadcast technology, has been developed by NHK (Japan Broadcasting Corporation). DARC is a registered trademark of NHK Engineering Service (NHK-ES). Any manufacturer licensed by NHK-ES can manufacture and sell products that utilize the DARC technology. The products utilizing the DARC technology can be marked with the logotype shown to the left. In the DARC system, 16kbps of digital data L-MSK modulated at 76KHz are multiplied on an ordinary FM broadcast base band signal. An FM multiplex demodulation LSI performs decoding of the digital data signal. For detailed information on license, please contact: NHK Engineering Service Phone: 81-3-3481-2650
E2Y0001-29-11
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents cotained herein may be reprinted or reproduced without our prior permission. MS-DOS is a registered trademark of Microsoft Corporation.
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Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan
CONTENTS 1. Modes
1.1 Operating Modes .............................................................................................................. 1 1.2 Frame Format ................................................................................................................... 1 Figure 1.1 Main Channel Mode Reception ............................................................ 2 Figure 1.2 Switched Reception Between Main Channel Mode and SubChannel Mode ...................................................................................... 3 Figure 1.3 Page Mode Reception .......................................................................... 4
2. Control Flow Examples
2.1 Normal Reception ............................................................................................................. 5 2.1.1 Total Flow ............................................................................................................... 5 2.1.2 Total Configuration ................................................................................................. 5 2.1.3 Interrupts ................................................................................................................. 5 2.1.4 User RAM Configuration ......................................................................................... 6 Table 2.1.4 User RAM Contents ............................................................................ 6 2.1.5 Description of Each Flow ........................................................................................ 7 Figure 2.1.1 Total Flow .......................................................................................... 8 Figure 2.1.2 Total Configuration ............................................................................ 9 Figure 2.1.3 Simplified Interrupt Flow .................................................................. 10 Figure 2.1.4 USR_RAM Configuration ................................................................. 11 Figure 2.1.5.1 Power-On Control Flow ................................................................ 12 Table 2.1 Recommended Parameter Setting Values .......................................... 13 Table 2.2 Registers That Do Not Require Parameter Setting .............................. 13 Figure 2.1.5.2 Initial Parameter Setting ............................................................... 14 Figure 2.1.5.3 Main Channel Activation ............................................................... 14 Figure 2.1.5.4 Main Channel Switched Reception ............................................... 14 Figure 2.1.5.5 Main Channel Halt ........................................................................ 15 Figure 2.1.5.6 Interrupt Control ............................................................................ 16 Figure 2.1.5.7 Receive _MAIN After 1st Horizontal Error Correction ................... 17 Figure 2.1.5.8 Reception After 2nd Horizontal Error Correction ........................... 18 Figure 2.1.5.9 Status Monitor .............................................................................. 19 2.2 Main/Sub Switched Reception ........................................................................................ 20 2.2.1 Total Flow ............................................................................................................. 20 2.2.2 Total Configuration ............................................................................................... 20 2.2.3 Interrupts ............................................................................................................... 21 2.2.4 User RAM Configuration ....................................................................................... 21 Table 2.2.4 User RAM Contents .......................................................................... 22 2.2.5 Description of Each Flow ...................................................................................... 23 Figure 2.2.1.1 Main/Sub Switched Reception Block Diagram ............................. 26 Figure 2.2.1.2 Total Flow ..................................................................................... 27 Figure 2.2.1.3-1/2 Main/Sub Switched Reception Timing .................................... 28 Figure 2.2.1.3-2/2 Main/Sub Switched Reception Timing .................................... 29 Figure 2.2.2 Total Configuration .......................................................................... 30 Figure 2.2.3 Simplified Interrupt Flow .................................................................. 31 Figure 2.2.4 USR_RAM Configuration ................................................................. 32 Figure 2.2.5.1 Power-On Control Flow ................................................................ 33 Table 2.3 Recommended Parameter Setting Values .......................................... 34 Table 2.4 Registers That Do Not Require Parameter Setting .............................. 34
Figure 2.2.5.2 Initial Parameter Setting ............................................................... 35 Figure 2.2.5.3 Main Channel Activation ............................................................... 35 Figure 2.2.5.4 Main Channel Switched Reception ............................................... 35 Figure 2.2.5.5 Sub Channel Activation ................................................................ 36 Figure 2.2.5.6 Halting the SUB Channel .............................................................. 37 Figure 2.2.5.7 Halting the Main Channel ............................................................. 38 Figure 2.2.5.8 Interrupt Control ............................................................................ 39 Figure 2.2.5.9 Frame Timing Setup _SUB ........................................................... 40 Figure 2.2.5.10 Reception After 2nd Horizontal Error Correction ........................ 41 Figure 2.2.5.11 Status Monitor ............................................................................ 42 Figure 2.2.5.12 SUB Control ................................................................................ 43 Figure 2.2.5.13 Sub Channel Connection ............................................................ 44 Figure 2.2.5.14 Receive _SUB After 1st Horizontal Error Correction ................... 45 Figure 2.2.5.15 Main Channel Connection .......................................................... 46 Figure 2.2.5.16 Bit Displacement Compensation ................................................ 47
MSM9562/63/66/67 User's Manual Control Flow
MSM9562/63/66/67 Control Flow 1. Modes
1.1 Operating Modes This IC has three reception modes. (1) A main channel mode (conventional method) that continuously receives data from a single broadcast station and outputs the received data in units of packets and frames (2) A sub-channel mode that receives data by switching a tuner at high-speed between one broadcast station (main station) and another broadcast station (sub-station), and outputs the sub-station receive data in packet units (During sub-station reception, missing main station packets can be regenerated by error correction. Therefore, by watching for missing packets, simultaneous reception of the main station and sub-station is possible.) A page mode that writes the 1st horizontal receive data to frame memory and outputs the collective packets receive during a specific time interval
(3)
Figures 1.1 to 1.3 show the receive operation of each receive mode. Applications of the sub-channel mode include simultaneous reception an FM multiplexed broadcast program on one channel and packet data on another channel. The page mode can be applied to pager or high-speed broadcast program verification. Each mode can be switched to another mode. 1.2 Frame Format This IC fully supports international standard frame formats A0, A1, B (Japan) and C. High-speed switching of each frame format is also possible.
1
F0: 1/2 frame reception Start reception
Receive packet 130 **** 271
Receive data
Timing interrupt 13_2
Interrupt
R_37 & 0x0F !=0
Receive data after 2nd horizontal error correction read Reference Flow Chart
, , , , , ,
MSM9562/63/66/67 User's Manual Control Flow
F1: 1 frame reception 0 **** 13 **** 270 271 0 **** 13 0 Receive interrupt Receive data after 1st horizontal error correction (SI = 1) *1 Receive interrupt Receive data after 1st horizontal error correction (SI = 1) Receive interrupt Receive data after 1st horizontal error correction (SI = 1) Receive interrupt Receive data after 1st horizontal error correction (SI = 1) Receive data after 2nd horizontal error correction *2 0 * * * * 94 Receive data after 2nd horizontal error correction F0 *1 Receive interrupt will not occur if all packet data of a frame cannot be received as indicated on the left, so the control according to the timing interrupt flow is necessary, as indicated in Reference Flow Chart. *2 Receive interrupt after 2nd horizontal error correction occurs after all packet data of a frame has been received as indicated on the right. 0 * * * * 95 * * * * 189 F1 189
2
Figure 1.1 Main Channel Mode Reception (Case where only SI = 1 at reception after the first horizontal error correction)
MAIN station
Receive data
SUB station
Tuner switching
, , ,,, , ,
1 frame reception 1 frame reception 0 **** 271 0 **** 13 **** 270 271 0 **** 13 0 Receive interrupt Receive data after 1st horizontal error correction Receive interrupt Receive data after 2nd horizontal error correction 0 * * * * 189 Receive interrupt Receive data after 2nd horizontal error correction 0 * * * * 189 Receive data _SUB after 1st horizontal error correction 0 Receive data _SUB after 1st horizontal error correction 0 Receive data _SUB after 1st horizontal error correction 1 Receive data _SUB after 1st horizontal error correction 1
3
MSM9562/63/66/67 User's Manual Control Flow
Receive interrupt 1
Receive interrupt 2
Receive interrupt 1
Receive interrupt 2
****
271
0
****
270
271
0
****
Tuner _MAIN
Tuner _SUB
Tuner _MAIN
Tuner _SUB
Tuner _MAIN
Figure 1.2 Switched Reception Between Main Channel Mode and Sub-Channel Mode
Block synchronization
****
271
****
****
270
Start reception
Timer interrupt
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Packet reception 271 0 **** 11 12 13 **** Frame memory 0 * * 11 Receive area Read receive data Timer interrupt User's work area
MSM9562/63/66/67 User's Manual Control Flow
4
Figure 1.3 Page Mode Reception
MSM9562/63/66/67 User's Manual Control Flow
2. Control Flow Examples
2.1 Normal Reception This flow example indicates the control flow of receive _MAIN after the 1st horizontal error correction, and of reception after the 2nd horizontal error correction. 2.1.1 Total Flow Figure 2.1.1 shows the total flow. The total flow can be changed by the following three controls. * Power-on/receive start (power-on 2/receive start 3) * Switching the MAIN channel * Halting operation 2.1.2 Total Configuration Figure 2.1.2 shows the total configuration. This figure shows the total flow control and the function of interrupts. Controls that manage the total flow such as MAIN reception or halting operation are executed from the main program. It is not necessary to synchronize these controls with the IC. The transfer of receive data (layer 3 data) after the 2nd horizontal error correction or receive _MAIN data after the 1st horizontal error correction to the USR_RAM, modification and display of this receive data, display of the synchronous state of the FM multiplexing IC, etc. are performed by interrupt control. This control must be synchronized with an IC interrupt. 2.1.3 Interrupts Figure 2.1.3 shows the flow of interrupt processing.
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MSM9562/63/66/67 User's Manual Control Flow 2.1.4 User RAM Configuration Figure 2.1.4 shows the configuration of user RAM and table 2.1.4 shows the contents of user RAM utilized in this flow. Table 2.1.4 User RAM Contents
1 2 3 4 5 6 7 8 9 10 (R_00) (R_01) (R_04) (R_05) (R_1A) (R_34) (R_37) PacketNo_MAIN 2nd horizontal data update flag N Content of interrupt register R_00 that was read Content of interrupt mask register R_01 that was written Content of channel connection register R_04 that was written Content of timing interrupt register R_05 that was written Display of frame sync monitor R_1A that was read (4 times/1 frame) Content of interrupt condition register R_34 that was written Display of receive status register R_37 (1 time/1 frame at receive interrupt after 2nd horizontal error correction) Packet number of main channel when an interrupt (main channel) is generated Display at completion of receive data read after 2nd horizontal error correction Number of block transfers 1 to 5: Receive data exists after 2nd horizontal error correction 0: No receive data after 2nd horizontal error correction 11 12 13 14 i 2nd j 1st horizontal USR_RAM horizontal USR_RAM 2nd horizontal error correction USR_RAM pointer To simplify explanation, cleared to "0" at reset Buffer area for receive data that was read after 2nd horizontal error correction 1st horizontal error correction USR_RAM_SUB pointer To simplify explanation, cleared to "0" at reset Buffer area for receive data that was read after 1st horizontal error correction
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MSM9562/63/66/67 User's Manual Control Flow 2.1.5 Description of Each Flow Control of the total flow is indicated in items (1) to (5). (1) Power-on control flow Shown in figure 2.1.5.1. Initial parameter setting Table 2.1 lists recommended parameter setting values and table 2.2 lists registers in which parameter setting is unnecessary. Figure 2.1.5.2 shows the parameter setting flow. MAIN channel activation Shown in figure 2.1.5.3. MAIN channel switching Shown in figure 2.1.5.4. MAIN channel halting Shown in figure 2.1.5.5.
(2)
(3)
(4)
(5)
Interrupt control of the MAIN channel is indicated in items (6) to (9). (6) Interrupt control Shown in figure 2.1.5.6. Receive _MAIN after 1st horizontal error correction Shown in figure 2.1.5.7. Reception after 2nd horizontal error correction Shown in figure 2.1.5.8. If there is a receive interrupt after the 2nd horizontal error correction, set the receive port (R_38) pointer to "0." Because the quantity of data is large, if the data cannot all be read at once (approx. 10 ms), divide it into several packets and then read the data. In this example, data is divided into N = 5 packets and is read five times. Interrupts are set at each packet timing. When N = 0 and the read is completed, interrupts are released at each packet timing, and after the 2nd horizontal error correction, update and display data is written.
(7)
(8)
(9) Status monitor Shown in figure 2.1.5.9.
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MSM9562/63/66/67 User's Manual Control Flow
(Total Flow)
Power off
Power-on 1 Receive start 1
Figure 2.2.5.1 Figure 2.2.5.1
MAIN channel switching Figure 2.1.5.4
MAIN reception
Figure 2.1.5.1
Receive start 2 Halt operation Figure 2.1.5.1
Figure 2.1.5.1
Power-on 3
Halt operation
Figure 2.1.1 Total Flow
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Power-on 1/ receive start 1
Power-on 1/receive start 1 MAIN channel switching CPU SUB channel activation
MAIN channel switching
SUB channel stop Halt operation
SUB channel activation
Power-on 3/receive start 2
Timing interrupt (4 times/frame)
USR_MEMORY (Update sync status, receive status and frame data)
SUB channel halt
Timing/ 0 Interrupt after 2nd horizontal error correction (5 times/frame) FM Multiplexed IC Receive data after 2nd horizontal error correction (frame data) 190 Receive data _MAIN after 1st horizontal error correction Receive interrupt_MAIN after 1st horizontal error correction
9
Halt operation Power-on 3/ receive start 2 Interrupts *Timing _MAIN *Receive _MAIN after 1st horizontal error correction *Receive _MAIN after 2nd horizontal error correction
MSM9562/63/66/67 User's Manual Control Flow
Program editing section
Figure 2.1.2 Total Configuration
MSM9562/63/66/67 User's Manual Control Flow
Interrupt
Clear interrupt
Receive interrupt _MAIN after 1st horizontal error correction
Receive and process _SUB after 1st horizontal error correction
Timing interrupt _MAIN
Receive and process after 2nd horizontal error correction
Return
Figure 2.1.3 Simplified Interrupt Flow
Case where receive _MAIN after 1st horizontal error correction and timing interrupt _MAIN occur in the same packet
Read reception after 1st horizontal error correction Read reception after 2nd horizontal error correction
0.4 ms 2 ms
Timing interrupt _MAIN
Receive interrupt _MAIN after 1st horizontal error correction
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MSM9562/63/66/67 User's Manual Control Flow
USR_RAM (R_00) Interrupt register contents (R_01) Interrupt mask (R_04) Connection channel (R_05) Timing interrupt control (R_1A) Frame sync monitor (R_34) Interrupt condition (R_37) Reception status (Note) Do not use with this flow (receive _MAIN after 1st horizontal error correction/after 2nd horizontal error correction)
Read/write contents of MSM956X registers
PacketNo_MAIN PacketNo_SUB Timer initial setting request _SUB Halt request _SUB Flags for control flow
PRE_BCK S D Data update flag after 2nd horizontal error correction Number of block transfers: N
2nd horizontal error correction USR_RAM pointer: i
Variables for phase compensation
Buffer for receive data after 2nd horizontal error correction USR_RAM after 2nd horizontal error correction
1st horizontal error correction USR_RAM pointer: j 1st horizontal error correction _MAIN USR_RAM 1st horizontal error correction _SUB USR_RAM pointer: k 1st horizontal error correction _SUB USR_RAM
Buffer for receive data after 1st horizontal error correction
Buffer for receive _SUB data after 1st horizontal error correction
Figure 2.1.4 USR_RAM Configuration 11
MSM9562/63/66/67 User's Manual Control Flow
Power-on 1
Receive start 1 Fig. 2.1.5.2 Parameter setting Fig. 2.1.5.3 MAIN channel activation
Power-down Fig. 2.1.5.5 MAIN channel halt
Receive start 2
Operation halt Fig. 2.1.5.5 MAIN channel halt
Power supply ON
External pin CLR
Power-off R_31 = 000
Fig. 2.1.5.3 MAIN channel activation
Analog/digital power-down R_31 = 004
Only oscillation circuit operates
Oscillation control ON R_31 = 004
Return
Return
Return
Return
25 msec Wait
Power-on 2
Power-on 3
12
Power-on R_31 = 007
Oscillation control ON R_31 = 004
Power-on R_31 = 007
Return
25 msec Wait
Return
Power-on R_31 = 007 XOUTC Return
Application example (1)
MSM956X
Open or "1"
Figure 2.1.5.1 Power-On Control Flow
MSM9562/63/66/67 User's Manual Control Flow Table 2.1 Recommended Parameter Setting Values
Register Interrupt mask Address 001
Setting value
Description Receive _MAIN after 1st horizontal error correction = timing _MAIN = "1" After 2nd horizontal error correction, setting is unnecessary since receive _MAIN and sync displacement are determined at time of R_00 read. 6 16 4/4MHz Before synchronization: 1 After synchronization: 2 SUB = 1 MAIN = 2 SUB = 4 MAIN = 15 1 4 1st horizontal error correction/2nd horizontal error correction mode DETO_DTST: invalid, ADETIN: invalid Amp gain: 3, DETTC: invalid PN decoding: on, Differential decoding: off, Monitor: off
036
Integration constant before block synchronization Integration constant after block synchronization
00C 00D 00E 010 011 012 018 019 028 030 033
006 010 033 009 012 04F 000 004 0A0 006 004
Phase correction step Allowable Number of BIC Error Bits
No. of Block Sync Backward Protection Steps No. of Block Sync Forward Protection Steps No. of Frame Sync Backward Protection Steps No. of Frame Sync Forward Protection Steps
DDJ mode * Analog TST1
* For MSM9566/67 only
Table 2.2 Registers That Do Not Require Parameter Setting
Register Address
Initial value
Description Use initial value of receive _MAIN after 1st horizontal error correction
Receive port switching 002 after 1st horizontal error correction
000
Main/sub channel switching
004
001 000 000 000 000 002
Use initial value of main channel (no switching) Setting unnecessary Setting unnecessary Setting unnecessary Setting unnecessary B format
Fixed phase adjustment 00B
Clear/set block sync 014 Clear sync Set sync Frame format Error correction 01B 01C 01F 020 to 022 025 03E
000 0FB 0EE 000
Not used Use initial value Use initial value Use initial value
Number of error corrections 023 Number of error corrections/threshold value
Operating mode
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MSM9562/63/66/67 User's Manual Control Flow
Initial parameter setting MAIN channel activation MAIN channel switching
R_0C = 006 R_0D = 010 R_0E = 033 R_10 = 009 R_11 = 012 R_12 = 04F R_18 = 000 R_19 = 004 R_28 = 0A0 R_30 = 006 R_33 = 004
MAIN connection
R_04 = (R_04) = 001
Main channel clear/release clear R_3E = 040 R_3E = 000
Timing interrupt setting Packet No.: 13 Byte No.: 2 Tuner switching R_05 = 001 R_16 = 010 R_17 = 000 R_1D = 00D R_1E = 000
R_05 = (R_05) = 003
Return
Interrupt condition after 1st horizontal error correction (SI = 1)
R_34 = 07A R_35 = 002 R_34 = 07B R_35 = 000
Figure 2.1.5.4 Main Channel Switched Reception
Interrupt mask *Receive _MAIN after 1st horizontal error correction *Timing interrupt _MAIN
R_01 = (R_01) = 022
Tuner ON
Return
Return
Figure 2.1.5.2 Initial Parameter Setting
Figure 2.1.5.3 Main Channel Activation
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MSM9562/63/66/67 User's Manual Control Flow
Halt MAIN channel
Interrupt mask
R_01 = (R_01) = 000
Disable timing interrupt
R_05 = (R_05) = 000
Main channel clear/release clear R_3E = 040 R_3E = 000
MAIN/SUB channel disconnect
R_04 = (R_04) = 000
Tuner OFF
Return
Figure 2.1.5.5 Main Channel Halt
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MSM9562/63/66/67 User's Manual Control Flow
Interrupt
Interrupt clear (R_00) = R_00 R_00 = (R_00) & (R_01)
Receive interrupt _MAIN after 1st horizontal error correction
(R_00) & 002 == 002
Fig. 2.1.5.7 Receive and process after 1st horizontal error correction
Timing interrupt _MAIN (R_00) & (R_01) & 020 == 20
Fig. 2.1.5.8 Receive and process after 2nd horizontal error correction
Return
Figure 2.1.5.6 Interrupt Control
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MSM9562/63/66/67 User's Manual Control Flow
Receive _MAIN after 1st horizontal error correction
Data read after 1st horizontal error correction USR_MEM[j++] = R_03
24-byte read
to reception after 2nd horizontal error correction
Figure 2.1.5.7 Receive _MAIN After 1st Horizontal Error Correction
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MSM9562/63/66/67 User's Manual Control Flow
Receive _MAIN after 2nd horizontal error correction
Packet number _MAIN PacketNo_MAIN = (R_1E & 001) *256 +R_1D
Status monitor
Fig. 2.1.5.9
Receive interrupt after 2nd horizontal error correction (R_00) & 010 == 010
N! = 0 Clear interrupt R_00 = 010
Address pointer
N=0
First byte number R_3B = 000 First packet number R_3C = 000 R_3D = 000
USR_RAM address
Data read after 2nd horizontal error correction USR_MEM[i++] = R_38
38*24 byte read
N=N-1 N == 0 N=0 Update and display data after 2nd horizontal error correction Release interrupt at each packet timing R_05 = 021 R_1E = 000 R_05 = (R_05) = 043 N! = 0
i=0
Number of split transfers
Number of block transfers N=5
Transfer timing
Set interrupt at each packet timing R_05 = 021 R_1E = 002 R_05 = (R_05) = 043
Return
Figure 2.1.5.8 Reception After 2nd Horizontal Error Correction
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MSM9562/63/66/67 User's Manual Control Flow
Status monitor
PacketNo_MAIN == 13 PacketNo_MAIN == 136 PacketNo_MAIN == 148 PacketNo_MAIN == 0
Timing interrupt setting Packet No.: 136 R_05 = 001 R_1D = 088 R_05 = (R_05) = 003
Timing interrupt setting Packet No.: 148 R_05 = 001 R_1D = 094 R_05 = (R_05) = 003
Timing interrupt setting Packet No.: 0 R_05 = 001 R_1D = 000 R_05 = (R_05) = 003
Timing interrupt setting Packet No.: 13 R_05 = 001 R_1D = 019 R_05 = (R_05) = 003
Receive status (R_37) = R_37 & 00F
Clear data update
Frame sync monitor (R_1A) = R_1A & 001
Return
Figure 2.1.5.9 Status Monitor
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MSM9562/63/66/67 User's Manual Control Flow 2.2 Main/Sub Switched Reception An example of the control flow of main/sub switched reception is listed below. (1) This example indicates the control flow of the receive _MAIN after the 2nd horizontal error correction and the receive _SUB after the 1st horizontal error correction. The receive _MAIN after the 1st horizontal error correction is omitted. (2) This example assumes that the sub-channel reception time includes: tuner switching time of 1x2 packets, clock capture time of 1/3 packet, and block synchronization time of 1 packet. In this case, 5.5 packets (including receive packet 2) disappear from the main channel. 2.2.1 Total Flow (1) (2) Figure 2.2.1.1 shows the block diagram. Figure 2.2.1.2 shows the total flow. The total flow can be changed by the following five controls * Power-on/receive start (power-on 2/receive start 3) * Switching the MAIN channel * Activating the SUB channel * Halting the SUB channel * Halting operation Figure 2.2.1.3-1/2 and figure 2.2.1.3-2/2 show the main/sub switching timing. Main channel packets are shown on the left and sub-channel packets on the right. To simplify this example, the packets have matching starting positions. In an actual application these positions are displaced, however details of the explanation do not change.
(3)
2.2.2 Total Configuration Figure 2.2.2 shows the total configuration. This figure shows the total flow control and the function of interrupts. Controls that manage the total flow such as MAIN reception, MAIN/SUB switched reception, halting operation, etc. are executed from the main program. It is not necessary to synchronize these controls to the IC. The transfer of receive data (Layer 3 data) after the 2nd horizontal error correction or of receive _SUB data after the 1st horizontal error correction to the USR_RAM, modification and display of this receive data, display of the synchronous state of the FM multiplexing IC, etc. are performed by interrupt control. This control must be synchronized with an IC interrupt.
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MSM9562/63/66/67 User's Manual Control Flow 2.2.3 Interrupts Figure 2.2.3 shows a simplified flow of interrupt processing. 2.2.4 User RAM Configuration Figure 2.2.4 shows the configuration of user RAM and table 2.2.4 shows the contents of user RAM utilized in this flow.
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MSM9562/63/66/67 User's Manual Control Flow Table 2.2.4 User RAM Contents
1 2 3 4 5 6 7 8 9 10 11 (R_00) (R_01) (R_04) (R_05) (R_1A) (R_34) (R_37) PacketNo_MAIN PacketNo_SUB Halt request _SUB PRE_BCK Content of interrupt register R_00 that was read Content of interrupt mask register R_01 that was written Content of channel connection register R_04 that was written Content of timing interrupt register R_05 that was written Display of frame sync monitor R_1A that was read (4 times/1 frame) Content of interrupt condition register R_34 that was written Display of receive status register R_37 (1 time/1 frame at receive interrupt after 2nd horizontal error correction) Packet number of main channel when an interrupt (main channel) is generated Packet number of sub channel when an interrupt (sub-channel) is generated Halt request flag for sub-channel reception Stores the bit number immediately prior to block synchronization of the sub-channel If there is no bit displacement, the value is 16. 12 13 14 15 D S 2nd N horizontal data update flag Stores the bit displacement D = PRE_BCK-16 Stores the bit displacement compensation value (S = S + D) Displayed at completion of receive data read after 2nd horizontal error correction Number of block transfers when reading data after the 2nd horizontal error correction. In this example, transfers are divided into N = 5 times. 1 to 5: Receive data exists after 2nd horizontal error correction 0: No receive data after 2nd horizontal error correction 16 17 18 19 i 2nd j 1st horizontal USR_RAM_SUB horizontal USR_RAM 2nd horizontal error correction USR_RAM pointer To simplify explanation, cleared to "0" at reset Buffer area for receive data after 2nd horizontal error correction that was read USR_RAM_SUB pointer after 1st horizontal error correction To simplify explanation, cleared to "0" at reset Buffer area for receive data SUB after 1st horizontal error correction that was read
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MSM9562/63/66/67 User's Manual Control Flow 2.2.5 Description of Each Flow Control of the total flow is indicated in items (1) to (7). (1) Power-on control flow Shown in figure 2.2.5.1. Initial parameter setting Table 2.3 lists recommended parameter setting values and table 2.4 lists registers in which parameter setting is unnecessary. Figure 2.2.5.2 shows the parameter setting flow. MAIN channel activation Shown in figure 2.2.5.3. MAIN channel switching Shown in figure 2.2.5.4. SUB channel activation Shown in figure 2.2.5.5. SUB channel halting Shown in figure 2.2.5.6. MAIN channel halting Shown in figure 2.2.5.7.
(2)
(3)
(4)
(5)
(6)
(7)
Interrupt control (8) Interrupt control Shown in figure 2.2.5.8. Interrupt control of the MAIN channel is indicated in items (9) to (11). (9) Frame timing setup _SUB Shown in figure 2.2.5.9. If (R_01) = 0x11(MAIN/SUB), since synchronization will be established for the first time with the SUB station, frame timing setup _SUB control is performed. The control flow initializes settings of the timer _SUB to the packet number of the synchronous SUB station. The packet number of the MAIN channel is set to the packet number counter (R_08, R_09) of the sub-channel so that the packet numbers are equal. Thereafter, use of timing interrupt _SUB is possible. Next, the timing is set to switch the tuner to the SUB station (packet number _SUB = 269, byte number = 22). Since frame timing setup _SUB is completed via the MAIN channel, reception with the MAIN channel is possible. After the 1st horizontal error correction, original receive conditions (R_34) are restored and the receive state of the SUB station is cleared (R_3E). The tuner switches to the MAIN channel and, continuing from step (8), processing of this interrupt is completed.
23
MSM9562/63/66/67 User's Manual Control Flow (10) Reception after 2nd horizontal error correction Shown in figure 2.2.5.10. If there is a receive interrupt after the 2nd horizontal error correction, set the receive port (R_38) pointer to "0". Since the quantity of data is large, if the data cannot be read at once (approx. 10 ms), divide it into several packets and then read the data. In this example, data is divided into N = 5 packets and is read. Interrupts are set at each packet timing. When N = 0 and the read is completed, interrupts are released at each packet timing, and after the 2nd horizontal error correction, update and display data is written. (11) Status monitor Shown in figure 2.2.5.11. Interrupt control of the SUB channel is indicated in items (12) to (16). (12) SUB control Shown in figure 2.2.5.12. Interrupt control of the SUB channel is activated by timer interrupt _SUB. Depending upon the packet number _SUB of the internal counter that is read, control switches to SUB connection, receive _SUB after 1st horizontal error correction, or main connection. (13) SUB connection Shown in figure 2.2.5.13. When the SUB station's packet number equals 269, control transfers to this flow. The channel is set to SUB connection and the tuner is switched from the MAIN station to the SUB station. Next, the receive timing of the 1st packet _SUB is set (packet number _SUB = 1, byte number = 2). The time until reception of the first packet _SUB consists of the following: tuner switch time, clock capture time, block sync time, and time required for reception of the first packet _SUB. (14) Receive _SUB after 1st horizontal error correction Shown in figure 2.2.5.14. When packet number of the SUB station equals 1 or 2, control transfers to this flow. When the receive interrupt is 1 after the 1st horizontal error correction, read 24 bytes of receive data. When the packet number of the SUB station equals 2, since the packets of the SUB channel are completed, execute various controls (synchronous clear _SUB, SUB disconnect, switch the tuner from the SUB station to the MAIN station) to complete processing of this interrupt. (15) MAIN channel connection Shown in figure 2.2.5.15. When the packet number of the SUB station equals 3, control transfers to this flow and connects the MAIN channel. When packet number _SUB equals 2, the switched tuner is stabilized and main channel reception can be resumed while maintaining the synchronous status when disconnected with a packet number of 269.
24
MSM9562/63/66/67 User's Manual Control Flow (16) Bit displacement compensation Shown in figure 2.2.5.16. After several consecutive frames, even if the packet number of the SUB station cannot be received, bit displacement compensation is performed to enable SUB connection with accurate timing. 7 bits can be compensated with 1 instruction. Bit compensation of up to 7 bits is implemented during the second packet reception of step (6). In the case of compensation of 8 bits or more, compensation of the remainder is implemented when MAIN channel connection of step (7) is 3. is the previous bit compensation number and is the bit displacement detected this time. Control of bit displacement compensation is required regardless of whether or not there is a receive packet.
25
MSM9562/63/66/67 User's Manual Control Flow
Timing interrupt SUB (R_00) Channel connect/disconnect _SUB (R_04) Clock regeneration _SUB Receive RAM _SUB after 1st horizontal error correction Receive RAM _MAIN after 1st horizontal error correction Frame memory Tuner switch _MAIN/SUB Channel connect/disconnect _MAIN (R04) Clock regeneration _MAIN Block sync _MAIN Frame sync _MAIN Timer _SUB
Bus
Block sync _SUB Receive RAM switch (R_02)
Tuner SUB station Equalization MAIN station
26
Tuner
Timer Timing interrupt _MAIN (R_00)
MSM956X
Figure 2.2.1.1. Main/Sub Switched Reception Block Diagram
Power off
Power-on 1 Receive start 1
Figure 2.2.5.1 Figure 2.2.5.1 Figure 2.2.5.5 SUB channel activation
MAIN channel switching Figure 2.2.5.4
MAIN reception
MAIN/SUB switched reception
SUB channel halt Figure 2.2.5.6 Figure 2.2.5.1 Receive start 2 MAIN channel halt Figure 2.2.5.1 Power-on 3
27
Halt operation
MSM9562/63/66/67 User's Manual Control Flow
Figure 2.2.5.7
Figure 2.2.1.2 Total Flow
,, ,,
Main channel station packet Sub channel station packet
MSM9562/63/66/67 User's Manual Control Flow
,,,,,,,,, ,,,,,,,,, ,,,,,,,,, ,,,,,, ,,,,,, ,,,,,,
Reception halt _MAIN Tuner switch time
Packet No. 130
131
,,,,,,,,, ,,,,,,,,, ,,,,,,,,, ,,,,,, ,,,,,, ,,,,,,
Non-receiving Tuner switch time/ clock capture time Fig. 2.2.5.5 SUB channel activation Reception in progress Frame synchronization
Frame timing detection/setting
136
,,,,,,,,,,,,, ,,,,,,,,,,,,, ,,,,,,,,,,,,,
Receive start _MAIN
137
,,,,,,,,,,,,, ,,,,,,,,,,,,, ,,,,,,,,,,,,,
Fig. 2.2.5.8/ Fig. 2.2.5.9 Frame timing setup _SUB * Initial timer setting * Tuner switch timing (to SUB) * Tuner reconnection (to MAIN)
28
,, ,, ,,
138
,, ,, ,,
Figure 2.2.1.3-1/2 Main/Sub Switched Reception Timing
,, ,, ,,
Main channel station packet Sub channel station packet
,,,, ,,,, ,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,,
Reception in progress _MAIN Tuner switch time Tuner switch time
269
Reception disconnect _MAIN
270
,,,,, ,,,,, ,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,,
Tuner switch time Block sync operation First packet Second packet
Fig. 2.2.5.8/ Fig. 2.2.5.12/ Fig. 2.2.5.13 * Channel connection _SUB * Tuner switching (to SUB) Tuner switch time + clock capture time
271
0
29
1
,,,,,,,,,,, ,,,,,,,,,,, ,,,,,,,,,,, ,,,, ,,,, ,,,,
Tuner switch time Tuner switch time Resume reception _MAIN
2
3
,,,,,,,,,,, ,,,,,,,,,,, ,,,,,,,,,,, ,,,, ,,,, ,,,,
Tuner switch time Tuner switch time Fig. 2.2.5.8/ Fig. 2.2.5.12/ Fig. 2.2.5.15 MAIN channel connection
Fig. 2.2.5.8/ Fig. 2.2.5.12/ Fig. 2.2.5.14 First packet reception
MSM9562/63/66/67 User's Manual Control Flow
Fig. 2.2.5.8/ Fig. 2.2.5.12/ Fig. 2.2.5.14 Second packet reception, Tuner switching (to MAIN)
Figure 2.2.1.3-2/2 Main/Sub Switched Reception Timing
MSM9562/63/66/67 User's Manual Control Flow
Power-on 1/ receive start 1
Power-on 1/receive start 1 MAIN channel switching CPU SUB channel activation
MAIN channel switching
SUB channel stop Halt operation
SUB channel activation
Power-on 3/receive start 2
Timing interrupt (4 times/frame)
USR_MEMORY (Updates of sync status, receive status and frame data)
SUB channel halt
Timing/ 0 Interrupt after 2nd horizontal error correction (5 times/frame) FM Multiplexed IC Receive data after 2nd horizontal error correction (frame data) 190 Receive data _SUB after 1st horizontal error correction Timing _SUB/1st horizontal _SUB interrupt (4 times/frame) Program editing section
30
Halt operation Power-on 3/ receive start 2 Interrupts *Timing _MAIN *Receive _MAIN after 2nd horizontal error correction *Timing _SUB *Receive _SUB after 1st horizontal error correction
Figure 2.2.2 Total Configuration
MSM9562/63/66/67 User's Manual Control Flow
tInterrupt
Clear interrupt
Receive interrupt _MAIN after 1st horizontal error correction & (MAIN/SUB connection)
Timer initial setting _SUB
Timing interrupt _MAIN
Receive and process after 2nd horizontal error correction
Timing interrupt _SUB
Sub channel control
Return
Figure 2.2.3 Simplified Interrupt Flow
31
MSM9562/63/66/67 User's Manual Control Flow
USR_RAM (R_00) Interrupt register contents (R_01) Interrupt mask (R_04) Connection channel (R_05) Timing interrupt control (R_1A) Frame sync monitor (R_34) Interrupt condition (R_37) Reception status
Read/write contents of MSM956X registers
PacketNo_MAIN PacketNo_SUB Timer initial setting request _SUB Halt request _SUB Flags for control flow
PRE_BCK S D Data update flag after 2nd horizontal error correction Number of block transfers: N USR_RAM pointer after 2nd horizontal error correction: i Buffer for receive data after 2nd horizontal error correction USR_RAM after 2nd horizontal error correction Variables for phase compensation
USR_RAM pointer after 1st horizontal error correction: j _MAIN USR_RAM after horizontal error correction 1st
Buffer for receive data after 1st horizontal error correction
_SUB USR_RAM pointer after 1st horizontal error correction: k _SUB USR_RAM after horizontal error correction 1st
Buffer for receive _SUB data after 1st horizontal error correction
Figure 2.2.4 USR_RAM Configuration 32
Power-on 1
Receive start 1 Fig. 2.2.5.2 Parameter setting Fig. 2.2.5.3 MAIN channel activation
Power-down Fig. 2.2.5.7 MAIN channel halt
Receive start 2
Operation halt Fig. 2.2.5.7 MAIN channel halt
Power supply ON
External pin CLR
Power-off R_31 = 004
Fig. 2.2.5.3 MAIN channel activation
Analog/digital power-down R_31 = 004
Only oscillation circuit operates
Oscillation control ON R_31 = 004
Return
Return
Return
Return
25 msec Wait
Power-on 2
Power-on 3
33
Power-on R_31 = 007
Oscillation control ON R_31 = 004
Power-on R_31 = 007
MSM9562/63/66/67 User's Manual Control Flow
Return
25 ms Wait
Return
Power-on R_31 = 007 XOUTC Return
Application example (1)
MSM956X
Open or "1"
Figure 2.2.5.1 Power-On Control Flow
MSM9562/63/66/67 User's Manual Control Flow Table 2.3 Recommended Parameter Setting Values
Register Interrupt mask Address 001
Setting value
Description Receive _MAIN after 1st horizontal error correction = timing _MAIN = "1" After 2nd horizontal error correction, setting is unnecessary since receive _MAIN and sync displacement are determined at time of R_00 read. 6 16 4/4MHz Before synchronization: 1 After synchronization: 2 SUB = 1 MAIN = 2 SUB = 4 MAIN = 15 1 4 1st horizontal error correction/2nd horizontal error correction mode DETO_DTST: invalid, ADETIN: invalid Amp gain: 3, DETTC: invalid PN decoding: on, Differential decoding: off, Monitor: off
036
Integration constant before block synchronization Integration constant after block synchronization
00C 00D 00E
006 010 033 009 012 04F 000 004 0A0 006 004
Phase correction step
No. of tolerable BIC errors 010
No. of protective steps at rear of block synchronization No. of protective steps at front of block synchronization No. of protective steps at rear of frame synchronization No. of protective steps at front of frame synchronization
011 012 018 019 028 030 033
DDJ mode * Analog TST1
* For MSM9566/67 only
Table 2.4 Registers That Do Not Require Parameter Setting
Register Address
Initial value
Description Use initial value of receive _MAIN after 1st horizontal error correction
Receive port switching 002 after 1st horizontal error correction
000
Main/sub channel switching
004
001 000 000 000 000 002
Use initial value of main channel (no switching) Setting unnecessary Setting unnecessary Setting unnecessary Setting unnecessary B format
Fixed phase adjustment 00B
Clear/set block sync 014 Clear sync Set sync Frame format Error correction 01B 01C 01F 020 to 022 025 03E
000 0FB 0EE 000
Not used Use initial value Use initial value Use initial value
Number of error corrections 023 Number of error corrections/threshold value
Operating mode
34
MSM9562/63/66/67 User's Manual Control Flow
q Initial parameter setting w MAIN channel activation e MAIN channel switching
R_01 = 030 R_0C = 006 R_0D = 010 R_0E = 033 R_10 = 009 R_11 = 012 R_12 = 04F R_18 = 000 R_19 = 004 R_28 = 0A0 R_30 = 006 R_33 = 004
MAIN connection R_04 = (R_04) = 001 Monitor/ receive CHK timing Frame interrupt setting Packet No.: 13 Byte No.: 2 R_05 = 001 R_16 = 010 R_17 = 000 R_1D = 00D R_1E = 000 R_05 = (R_05) = 003
Main channel clear/release clear R_3E = 040 R_3E = 000
Tuner switching
Return
Return
Figure 2.2.5.2 Initial Parameter Setting
Interrupt mask R_01 = (R_01) = 020
Figure 2.2.5.4 Main Channel Switched Reception
Tuner ON
Return
Figure 2.2.5.3 Main Channel Activation
35
MSM9562/63/66/67 User's Manual Control Flow
SUB channel activation
Preparations for connection to SUB station
MAIN_CH clear/ release clear R_3E = 040 R_3E = 000
Interrupt mask Add receive _MAIN after 1st horizontal error correction R_01 = (R_01) = 022
Receive interrupt condition setting _SUB after 1st horizontal error correction * All SI specified * Frame synchronization R_34 = (R_34) = 0A0
Channel connection (MOD_MAIN/SUB) R_04 = (R_04) = 011
Tuner switching (to SUB station)
Return
Figure 2.2.5.5 Sub Channel Activation
36
MSM9562/63/66/67 User's Manual Control Flow
Activation of SUB Channel Halt
SUB channel reception is halted while maintaining the receive state of the MAIN channel. (1) In the state where "PacketNo = 269 or 1 or 2", the tuner is connected to the SUB station. Control is performed as follows: q the MAIN/SUB channel is disconnected, w the tuner is switched to the MAIN station, and e after the tuner switch time elapses, the MAIN channel is reconnected. Processes q and w are executed with the flow shown below on the left. Process e is executed within the "figure 2.2.5.15 Main Connection" interrupt routine. After executing the interrupt of process e, SUB channel reception is halted. (2) In the state where "PacketNo ! = 269 or 1 or 2", the tuner is not connected to the SUB station. Therefore, after the timing interrupt _SUB is halted and the SUB channel is disconnected, SUB channel reception is halted.
Activation of SUB Channel halt
PacketNo_SUB == 269 or 1 or 2
Halt request _SUB = 1
Disable timing interrupt _SUB R_05 = (R_05) = 023
MAIN/SUB switching R_04 = (R_04) = 000
Connect MAIN Disconnect SUB R_04 = (R_04) = 001
Switch tuner to MAIN
Interrupt mask Disable receive _SUB after 1st horizontal error correction R_01 = (R_01) = 020
Return
Figure 2.2.5.6 Halting the SUB Channel 37
MSM9562/63/66/67 User's Manual Control Flow
Halt MAIN channel
Interrupt mask R_01 = (R_01) = 000
Disable timing interrupt R_05 = (R_05) = 021
Main channel clear/release clear R_3E = 040 R_3E = 000
MAIN/SUB channel disconnect R_04 = (R_04) = 000
Tuner OFF
Return
Figure 2.2.5.7 Halting the Main Channel
38
MSM9562/63/66/67 User's Manual Control Flow
Interrupt
Clear interrupt (R_00) = R_00 R_00 = (R_00) & (R_01)
Receive interrupt _MAIN after 1st horizontal error correction && (MAIN/SUB connect)
(R_00) & (R_01) & 002 == 02 && (R_04) == 011)
Fig. 2.2.5.9 Timer initial setting _SUB Timing interrupt _MAIN (R_00) & (R_01) & 020 == 20
Fig. 2.2.5.10 Receive and process after 2nd horizontal error correction
Timing interrupt _SUB (R_00) & (R_01) & 040 == 40
Fig. 2.2.5.12 Sub channel control
Return
Figure 2.2.5.8 Interrupt Control
39
MSM9562/63/66/67 User's Manual Control Flow
Frame Timing Setup _SUB (Frame timing detection/setup _SUB) Timer initial setting _SUB
Timer initial setting Frame timing counter initial setting _SUB (counter value _MAIN AE counter value _SUB) R_05 = 011 R_08 = R_1D R_09 = (R_1E & 001)
MAIN connection R_04 = (R_04) = 001
MAIN_CH clear/ release clear R_3E = 040 R_3E = 000
Tuner _SUB switch timing Timing interrupt setting _SUB (for tuner switching) Packet No.: 269 Byte No.: 22 R_05 = 021 R_06 = 0B0 R_07 = 000 R_08 = 00D R_09 = 001 R_05 = (R_05) = 063
Receive interrupt condition after 1st horizontal error correction (All synchronously received packets) R_34 = (R_34) = 020
Interrupt mask (disable receive _MAIN after 1st horizontal error correction)
R_01 = (R_01) = 060
Switch tuner to MAIN station
Return
Figure 2.2.5.9 Frame Timing Setup _SUB
40
MSM9562/63/66/67 User's Manual Control Flow
!2Receive _MAIN after 2nd horizontal error correction Packet number _MAIN PacketNo_MAIN = (R_1E & 001) *256 +R_1D Fig. 2.2.5.11 Status monitor
Receive interrupt after 2nd horizontal error correction (R_00) & 010 == 010 N! = 0 Clear interrupt R_00 = 010
Address pointer
N=0
First byte number R_3B = 000 First packet number R_3C = 000 R_3D = 000
USR_RAM address
Data read after 2nd horizontal error correction USR_MEM[i++] = R_38
38*24 byte read
N = N-1 N == 0 N=0 Update and display data after 2nd horizontal error correction N! = 0
i=0
Number of split transfers
Number of block transfers N=5
Transfer timing
Set interrupt at each packet timing Byte No.: 4 R_05 = 021 R_16 = 010 R_1E = 002 R_05 = (R_05) = 063
Release interrupt at each packet timing R_05 = 021 R_1E = 000 R_05 = (R_05) = 063
return (Preparation for data read) (Data read)
Figure 2.2.5.10 Reception After 2nd Horizontal Error Correction
41
MSM9562/63/66/67 User's Manual Control Flow
Status monitor
PacketNo_MAIN == 13 PacketNo_MAIN == 136 PacketNo_MAIN == 148 PacketNo_MAIN == 0
Timing interrupt setting Packet No.: 136 Byte No.: 2 R_05 = 021 R_16 = 010 R_1D = 088 R_1E = 000 R_05 = (R_05) = 063
Timing interrupt setting Packet No.: 148 Byte No.: 2 R_05 = 021 R_16 = 010 R_1D = 094 R_1E = 000 R_05 = (R_05) = 063
Timing interrupt setting Packet No.: 0 Byte No.: 2 R_05 = 021 R_16 = 010 R_1D = 000 R_1E = 000 R_05 = (R_05) = 063
Timing interrupt setting Packet No.: 13 Byte No.: 2 R_05 = 021 R_16 = 010 R_1D = 019 R_1E = 000 R_05 = (R_05) = 063
Receive status (R_37) = R_37 & 00F
Clear data update
Frame sync monitor (R_1A) = R_1A & 001
Return
Figure 2.2.5.11 Status Monitor
42
MSM9562/63/66/67 User's Manual Control Flow
SUB control
Packet number _SUB * PacketNo_SUB = (R_09 & 001) *256 +R_08
PacketNo_SUB == 269
PacketNo_SUB == 1 or 2
PacketNo_SUB == 3
Fig. 2.2.5.13 Sub-Channel connection
Fig. 2.2.5.14 Receive _SUB after 1st horizontal error correction
Fig. 2.2.5.15 Main connect _SUB
Return
Figure 2.2.5.12 SUB Control
43
MSM9562/63/66/67 User's Manual Control Flow
SUB Channel Connection
SUB channel connection
Channel connection _SUB MAIN disconnect SUB connect R_04 = (R_04) = 010
Timing interrupt setting _SUB (for 1st packet reception) Packet No.: 1 Byte No.: 2 R_05 = 023 R_06 = 010 R_07 = 000 R_08 = 001 R_09 = 000 R_05 = (R_05) = 063
Switch tuner to SUB station
Return
Figure 2.2.5.13 Sub Channel Connection
44
MSM9562/63/66/67 User's Manual Control Flow
Receive _SUB after 1st horizontal error correction
Receive interrupt _SUB after 1st horizontal error correction (R_00) & 080 == 080
Reception processing
PacketNo_SUB == 1 PacketNo_SUB = 1 PacketNo_SUB = 2
Clear receive _SUB after 1st horizontal error correction R_00 = 080 horizontal error correction RAM select R_02 = 001 Data read after 1st horizontal error correction USR_MEM = R_03 1st
Timing interrupt _SUB for 2nd packet reception (Packet No.: 2) (Byte No.: 2) R_05 = 023 R_06 = 010 R_07 = 000 R_08 = 002 R_09 = 000 R_05 = (R_05) = 063
Timing interrupt _SUB for MAIN connection (Packet No.: 3) (Byte No.: 2) R_05 = 023 R_06 = 010 R_07 = 000 R_08 = 003 R_09 = 000 R_05 = (R_05) = 063
24-byte read Synchronous clear _SUB R_14 = 020
MAIN/SUB disconnect R_04 = (R_04) = 000 Fig. 2.2.5.16
Phase compensation _1
Switch tuner to MAIN
Return
Figure 2.2.5.14 Receive _SUB After 1st Horizontal Error Correction
45
MSM9562/63/66/67 User's Manual Control Flow
Main Connection
Main connection PacketNo_SUB = 3 Channel connection _MAIN MAIN connection R_04 = (R_04) = 001
Tuner switching _SUB Timing setup Timing interrupt _SUB for tuner switching (Packet No.: 269) (Byte No.: 22) R_05 = 023 R_06 = 0B0 R_07 = 000 R_08 = 00D R_09 = 001 No Halt request _SUB == 1 Yes Halt request _SUB = 0
Timing interrupt _SUB R_05 = (R_05) = 023
Timing interrupt _SUB R_05 = (R_05) = 063
Interrupt mask Disable receive _SUB after 1st horizontal error correction R_01 = (R_01) = 030 Fig. 2.2.5.16 Phase compensation _2
Return
Figure 2.2.5.15 Main Channel Connection
46
MSM9562/63/66/67 User's Manual Control Flow
Phase Compensation _SUB (Note 1) Phase compensation _1 (Note 1) Phase compensation _2
Bit no. immediately before synchronization
abs (S) > 7
PRE_BCK = (R_07 & 001) *256 +R_06 S>0 PRE_BCK > 32 (Note 2) Since displacement is large, go to resynchronization To resynchronization setting (Note 3)
Total no. of compensation bits
Add S bits R_0A = 008 S
Remove S bits R_0A = abs (S)
No. of compensation bits D = 16-PRE_BCK
Return
S=S+D
abs (S) > 7
S>0
S>0
Add 7 bits R_0A = 00F
Remove 7 bits R_0A = 007
Add S bits R_0A = 008 S
Remove S bits R_0A = abs (S)
Return
Figure 2.2.5.16 Bit Displacement Compensation (Note 1) (Note 2) (Note 3) In this flow, since bit correction of the sub channel is divided and performed in 2 operations, correction of up to 14 bits (max.) is possible. Correction is necessary 2 or more times. Alternatively, the packet number may be displaced. Implement sub channel activation processing after the sub channel is haltted. 47
MSM9562/63/66/67 User's Manual Control Flow
48

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